This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-333377, filed Nov. 24, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a computer system, and, more particularly, to an improved computer system which connects two buses by a serial transfer line.
Recently have been developed various notebook type personal computers (hereinafter called xe2x80x9cnotebook PCsxe2x80x9d) which are easy to carry around and operatable on a battery. Some notebook PCs are so designed as to be able to attach to an expansion unit, as needed, in order to expand the functions. To effectively use resources of the expansion unit from a notebook PC body, it is important to connect a bus in the notebook PC body to a bus in the expansion unit. This bus interconnection can allow devices on the bus in the expansion unit to be treated like devices in the notebook PC body.
Many personal computers employ a PCI (Peripheral Component Interconnect) bus. Therefore, bus interconnection between a notebook PC body and an expansion unit is normally accomplished by providing the notebook PC body and the expansion unit with docking connectors each having multiple pins equivalent in number to signal lines of a PCI bus and physically connecting the PCI buses of both the notebook PC body and expansion unit via the docking connectors.
Because this structure needs a large mount area for the docking connector, it is disadvantageous in making notebook PC bodies more compact and flatter. Further, the mount position for the docking connector on a notebook PC body should aligned with the mount position for the docking connector on an expansion unit. This puts some restriction on the physical casing structures of new products which are being developed.
U.S. Pat. Nos. 5,457,785, 5,579,489 and 5,619,659 disclose a scheme of connecting a PC body to an expansion unit by using the standard parallel port of the PC body. According to this scheme, an ISA bus is formed in an expansion unit, which is connected to a PC body by a cable, via the standard parallel port of the PC body and the ISA bus in the expansion unit is allowed to perform the same operation as the ISA bus in the PC using a circuit which interprets the signal status of the ISA bus in the PC body.
Another U.S. Pat. No. 5,822,571 discloses the structure wherein a primary PCI bus is connected to a secondary PCI bus by a flat cable and a PCI bus extends from a PC body to another casing, and a method for clock synchronization which copes with transfer delay in the cable.
As those conventional cable-based interconnecting methods carries out parallel data transfer over a cable, however, the cable contains many signal lines. In particular, exclusive signal lines for transferring interrupt signals are provided in addition to signal lines for an address, command, data and so forth, thus making the total number of signal lines extremely large. This leads to the following shortcomings.
1) The cable becomes thicker and harder to handle and the cost gets higher.
2) The number of pins of a connector for cable connection increases, which results in a higher cost and stands in the way of making a notebook PC compact.
Accordingly, it is an object of the present invention to provide a computer system which can transfer data needed to transfer a bus cycle between buses and an interrupt signal in the same transfer line, thus permitting a host system to be connected to an expansion unit by a cable having fewer signal lines.
To achieve the above object, according to one aspect of this invention, there is provided a computer system comprising a first bus for transferring a first interrupt signal; a second bus for transferring a second interrupt signal; a first controller connected to the first bus; a second controller, connected to the second bus, executing a transfer cycle including a bus cycle with the first controller means for coupling the first controller with the second controller; means, connected to the first controller, for generating control data indicating a state of the first interrupt signal on the first bus; and means, connected to the second controller, for outputting a second interrupt signal on the second bus based on the control data.
It is preferable that the transfer cycle is a serial transfer cycle.
In this computer system, the data transfer means for interconnecting two (first and second) buses is separated into two physically different controllers to execute the transfer cycle, desirable serial transfer cycle. This transfer cycle accomplishes exchange of data needed to transfer a bus cycle, such as a command, address and data, between the two controllers. With regard to an interrupt signal, control data indicating the state of the interrupt signal is inserted in the transfer cycle for transferring data of a bus cycle and then transferred. This can permit transfer of both data needed to transfer a bus cycle and an interrupt signal via the same transfer line or the like. Therefore, providing each of a host system and an expansion unit with two controllers which constitute a bus bridge, for example, can permit the host system to be connected to the expansion unit by a cable with fewer signal lines.
The host system is not limited to a computer body itself. For example, a computer body may be connected to a first expansion unit through which a second expansion unit is connected to the computer body. In this case, as seen from the second expansion unit, the computer body and the first expansion unit serve as a host system.
The means for generating the control data is characterized by detecting a change in the first interrupt signal on the first bus, and generates control data indicating the state of the first interrupt signal and inserts the control data into the serial transfer cycle when detecting the change in the first interrupt signal. As control data indicating the state of an interrupt signal is serially transferred only when the state of this interrupt signal has been changed, the throughput of serial transfer for transferring a bus cycle will not be affected.
In the case of using this structure that executes serial transfer of control data when the state of an interrupt signal has been changed, it is preferable that the means for generating the control data should have a latch circuit for holding a state of the second interrupt signal until receiving new control data indicating a state of a next first interrupt signal. With regard even to a level triggered interrupt signal, like a PCI bus interrupt signal, whose level should be held until the interrupt signal is received by software, therefore, the system can accurately be informed of the occurrence of interruption merely by serially transferring control data only when the state of the interrupt signal has been changed.
Further, in the case where control data is serially transferred when the state of an interrupt signal has been changed, the event of occurrence of an interrupt signal is immediately notified to the software. It is therefore preferable to provide for arbitrating all data transferred via the serial transfer line in such a way that the control data is serially transferred with a highest priority over other data when there are plural kinds of data to be serially transferred in the serial transfer cycle.
Even in the case where data is transferred in parallel between the controllers, transferring the state of an interrupt signal via the data transfer line can eliminate the need for a special transfer line for the interrupt signal. This can contribute to reducing the number of signal lines. In other words, the fundamental concept of this invention is the transfer of the state of an interrupt signal itself as one of bus transactions in order to reduce the number of signal lines. While it is most effective to adapt this structure to a bus bridge, this invention may also be adapted to transfer of an interrupt signal from a first interruption controller connected to one of two buses to a second interruption controller connected to the other bus.
To achieve the above object, according to another aspect of this invention, there is provided a data transfer method comprising: the step of detecting a first interrupt signal on a first bus; generating control data indicating a state of the first interrupt signal in response to the detection of the first interrupt signal; transferring the control data to a second bus by interrupting the control data into serial transfer cycle which includes a bus cycle between the first bus and the second bus; and outputting a second interrupt signal on the second bus based on the control data in such a way that the first interrupt signal is reflected on the second bus.
In this data transfer method, the control data in response to detection of the first interrupt signal is generated and transferred to the second bus by interruption into serial transfer cycle, which includes a bus cycle between the first bus and the second bus. The second interrupt signal is outputted on the second bus based on the control data in such a way that the first interrupt signal is reflected on the second bus. Consequently, the transfer cycle executed between the first bus and the second bus accomplishes exchange of data needed to transfer a bus cycle, such as a command, address and data, between the two controllers. In addition, with regard to an interrupt signal, control data indicating the state of the interrupt signal is inserted in the transfer cycle for transferring data of a bus cycle and then transferred. This can permit transfer of both data needed to transfer a bus cycle and an interrupt signal via the same transfer line or the like. Therefore, providing each of a host system and an expansion unit with two controllers which constitute a bus bridge, for example, can permit the host system to be connected to the expansion unit by a cable with fewer signal lines.
The host system is not limited to a computer body itself. For example, a computer body may be connected to a first expansion unit through which a second expansion unit is connected to the computer body. In this case, as seen from the second expansion unit, the computer body and the first expansion unit serve as a host system.
The first bus transfers a first plurality of interrupt signals; the second bus transfers a second plurality of interrupt signals; and the step of generating control data includes the steps of: detecting a change in the first interrupt signal on the first bus; and generating the control data including a bit pattern corresponding to the first plurality of interrupt signals on the first bus when the change in the first interrupt signal on the first bus has been detected. As control data indicating the state of an interrupt signal is serially transferred only the state of this interrupt signal has been changed, the throughput of serial transfer for transferring a bus cycle will not be affected.
In the case of using this structure that executes serial transfer of control data when the state of an interrupt signal has been changed, it is preferable that the second interrupt signal should be held by a latch circuit until receiving new control data indicating a state of a next first interrupt signal. With regard even to a level triggered interrupt signal, like a PCI bus interrupt signal, whose level should be held until the interrupt signal is received by software, therefore, the system can accurately be informed of the occurrence of interruption merely by serially transferring control data only when the state of the interrupt signal has been changed.
Further, in the case where control data is serially transferred when the state of an interrupt signal has been changed, the event of occurrence of an interrupt signal is immediately notified to the software. It is therefore preferable to provide for the step of arbitrating all data transferred via the serial transfer cycle in such a way that the control data is serially transferred with a highest priority over other data when there are plural kinds of data to be serially transferred in the serial transfer cycle.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.